At the SMTA International 2019 technical conference, which will be held September 22-26 in Rosemont, Ill., Portland State University and Zymet will present their investigations on enhancing the board-level reliability of large wafer-level packages (WLPs) for harsh environment applications. The paper, “Multi-Axis Loading Effect on Edgebond and Edgefilled WLCSP Thermal Cycling Performance,” will be presented on September 25 at Session APT4: Wafer Level Packaging.

WLPs, which include wafer-level chip-scale packages (WLCSPs) and fan-out wafer-level packages (FO-WLPs), offer a path to lower weight, smaller form factor, and higher performance. However, their low coefficient of thermal expansions are not well matched to that of commonly used organic substrates. This mismatch results in early solder joint fatigue and early failures in thermal cycle tests, which become increasingly difficult to pass as the package gets larger and the conditions become more severe. This limitation constricts package designers to using either smaller package sizes or to limiting the use of such packages to less-severe environments. The investigation reportedly shows that reworkable adhesives can enhance the board-level reliability of large WLPs, even for harsh environment applications.